1. Technical Field of the Invention
The present invention generally relates to domain of phase locked loops, and particularly phase locked loops made in the form of an integrated circuit and that are typically used in high frequency synthesis. More precisely, it concerns a frequency synthesizer enabling precise adjustment of the frequency, with a high signal-to-noise ratio and with advanced integration capabilities.
2. Description of Related Art
A Phase Locked Loop (PLL) is generally widely used for frequency synthesis. This type of system is capable of multiplying a reference frequency by an integer number and thus addressing an entire frequency range with a given frequency step. More precisely, a phase locked loop is a slaving system generating a frequency equal to the K times the reference frequency that it receives in input. Thus, the output frequency given by a voltage controlled oscillator is divided and then compared with a frequency that may be produced by a quartz. A charge pump formed from two current sources then reacts by injecting or withdrawing current in an integrating filter that controls the output oscillator.
However, in order to obtain a finer output frequency from the frequency synthesizer and therefore a lower frequency resolution, it is necessary to use “fractional” phase locked loops in order to make a division with a decimal part. Such frequency synthesizers can thus be used to generate frequencies that can be adjusted by integer or non-integer multiples of a reference frequency.
Such devices like those described above are known. FIG. 1 represents a conventional frequency synthesizer that can be adjusted by integer values, and FIG. 2 represents a frequency synthesizer that can be adjusted by fractional values.
Therefore, FIG. 1 illustrates the structure of a frequency synthesizer designed for high-frequency synthesis based on a programmable standard phase locked loop 10. The phase locked loop 10 essentially comprises a voltage controlled oscillator (VCO) 12, a frequency divider 14, a phase—frequency comparator (PFD) 16, a charge pump (CP) circuit 18 and a low-pass integrating filter (LPF) 20. The voltage controlled oscillator 12 outputs an output signal Fvco with a frequency of the order of one Giga hertz and that can be increased or reduced as a function of a control voltage applied to its input. This control voltage is generated by the phase—frequency comparator 16 and the charge pump circuit 18 connected to the input of the oscillator 12 through the loop filter 18. The phase—frequency comparator compares the frequency Fpfd (and/or the phase) of a signal output by the frequency divider 14 and the frequency of a reference signal Fref, for example produced by a quartz device. For feasibility of the system, given the high frequency synthesis context, a pre-divider circuit 26 may be integrated into the loop 10 between the oscillator 12 and the frequency divider 14. This circuit 26 is used to introduce a frequency division factor S applied to the frequency signal Fvco before being input to the frequency divider 14.
A frequency divider 22 may be inserted between the quartz device and the phase—frequency comparator 16, such that the phase—frequency comparator compares the signal Fpfd with a frequency signal Fin equal to a division by a predetermined factor R of the frequency of the signal Fref. An adjustment input 22a fixes the value R. Thus, the phase comparator can be made to operate at a much lower frequency than the quartz.
When the frequency of the signal produced by the frequency divider 14 is less than the frequency of the reference signal Fin, the phase—frequency comparator 16 controls the charge pump circuit 18 which, associated with the loop filter 20, outputs a voltage controlling the increase in the frequency of the oscillator 12. Conversely, the frequency of the oscillator 12 is reduced when the frequency of the signal output by the frequency divider 14 is greater than the frequency of the signal Fin.
The frequency divider 14 is a device that divides the frequency of the signal from the oscillator 12 only by integer values. Therefore the division ratio that can be adjusted by integer values, is an integer number denoted N. An adjustment input 14a fixes this division ratio.
Also, a frequency divider 24 may be inserted at the output from the oscillator 12, so as to obtain an output signal from the frequency synthesizer for which the frequency Fout is equal to a division by a predetermined factor P of the frequency of the signal Fvco output from the oscillator. An adjustment input 24a fixes the value P.
Therefore the synthesizer output frequency, denoted Fout, is such that:
  Fout  =            SxN      P        ×    Fin  and the frequency step at the output from the oscillator 12 is such that:ΔFvco=SxFinwhere Fin=Fref/R.
Therefore the oscillation frequency of the voltage controlled oscillator may be adjusted by frequency steps with a value equal to Fin, ignoring the factor S. The step then corresponds to a variation of the division ratio from N to N+1, or from N to N−1. To obtain a low frequency step and therefore a relatively precise adjustment of the loop frequency, the value of the frequency of the reference signal should be preferably chosen low, of the order of a few tens of kilo Hertz, for example. This means that a very large loop filter is required to keep the PLL stable. But such a filter makes it impossible to use integratable solutions. Note also that a low reference frequency makes it necessary to select high values N of the division ratio, which causes noise in the loop and degrades expected performances.
A much finer adjustment of the frequency of the output signal produced by the voltage controlled oscillator may be obtained without the above mentioned disadvantage with the constraint of the choice of a relatively low value for the reference frequency, with a frequency synthesizer conforming with FIG. 2.
The synthesizer in FIG. 2 comprises a phase locked loop 10 in which the elements in common with the elements in loop 10 in FIG. 1 have the same reference.
On the other hand, the frequency divider 14 not only has an adjustment input 14a to fix the value of the division ratio N, but it also has a switching input 14b to switch the division ratio about the value N between two or more consecutive values, for example between two values equal to N and N+1. The switching input 14b is connected to a sigma-delta modulator 30 in the form of a order 1, 2 or 3 digital modulator that modifies the division ratio at the divider 14. The sigma-delta modulator 30 has a first digital input 30a on which an adjustment set value denoted K coded on u bits is applied. It comprises a second input 30b connected to the output from the divider 14, for which the output signal is used to clock the modulator.
The frequency divider 14 is designed to make a frequency division with a first division ratio when its switching input 14b receives a first logical state output by the sigma-delta modulator and so as to make a division with a second division ratio when the input 14b receives a second logical switching state of the sigma-delta modulator. For example, the division ratio is N for the first logical state and N+1 for the second logical state. Although the division ratio of the frequency divider 14 is an integer number at all times, repeated switching of the ratio between N and N+1 can result in an average resulting division ratio α between these two values, in other words a non-integer number.
More precisely, considering that the adjustment set value K applied to the first input 13a of the sigma-delta modulator is coded on u bits, a fractional part of the division ratio of the divider 14 made by the modulator can be defined equal to
      K          2      u        .
Thus, the division ratio α including the integer part N and the fractional part produced by the modulator, can be written:
  α  =      N    +                  K                  2          u                    .      Therefore the output frequency from the synthesizer is such that:
  Fout  =                    α        ⁢                                  ⁢        xS            P        ×    Fin  and the output frequency step from the voltage controlled oscillator is:
      Δ    ⁢                  ⁢    Fvco    =            SxFin              2        u              .  
Thus, the frequency of the phase locked loop can be continuously adjusted between two values fixed by the choice of the division ratio N applied to the adjustment input 14a of the frequency divider 14 and by the choice of the adjustment set value K applied to the sigma-delta modulator. The result of the above formula is that the adjustment step can be as fine as Fin/2u, within a factor S. For coding the adjustment set value K of the sigma-delta modulator on 8 or 16 bits, in other words for example for u=8 or u=16, the adjustment may be almost continuous and therefore practically independently of the reference frequency. Therefore, due to the algorithm used by the sigma-delta modulator, this solution can give good resolution without needing to drop to a low reference frequency, as for the first solution.
However, the sigma-delta modulator generates a high noise power in the loop that can cause undesirable fluctuations of the phase of the signal output by the voltage controlled oscillator. This behavior will degrade the signal-to-noise ratio of the system, although a high signal-to-noise ratio is absolutely necessary to guarantee good system performances, particularly for wide band applications.
Noise introduced by the sigma-delta modulator algorithm can be compensated by making the cutoff low at the loop filter, so as to reject a maximum amount of noise from the useful frequency band. However, if the cutoff frequency of the loop filter is reduced for this purpose, the phase noise from the voltage controlled oscillator becomes too important with regard to the expected performances of the system, particularly in the context of wide band applications in which such synthesizers are used. Therefore the architecture presented with reference to FIG. 2 makes it very difficult to obtain an acceptable compromise between noise from the sigma-delta modulator algorithm and phase noise from the voltage controlled oscillator.
A need accordingly exists for a new frequency synthesizer architecture without the limitations mentioned above related to the frequency synthesizer architectures according to prior art.